The present invention relates generally to non-volatile memory devices. More particularly, the present invention relates to improved methods of operating a NAND array comprising a plurality of localized trapped charge memory cell structures capable of storing multiple bits per cell.
Recently, a new type of memory cell, known as PHINES (Programming by hot Hole Injection Nitride Electron Storage) and which is described in detail in C. C. Yeh et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch 2-Bit per Cell Flash Memory,” IEDM, p. 931, 2002, has been introduced. FIG. 1 depicts such a PHINES memory cell or transistor 10 that is implemented in and on substrate 8. Memory cell 10 comprises source and drain regions 22, 24, as is conventional in a typical MOSFET structure, and a channel 12 disposed between source and drain regions 22, 24. Overlying channel 12 is a unique charge-trapping structure 11, which comprises a charge-trapping nitride layer 16 (e.g., silicon nitride) disposed between two oxide isolation layers 14, 18 (e.g., silicon oxide). Each memory cell 10 further comprises a gate electrode 20 that overlies the charge-trapping structure 11, and the source and drain regions 22, 24 each has a corresponding electrode, as shown in FIG. 1.
As is explained more fully below, by properly manipulating the relative voltages among substrate 8, source and drain regions 22, 24 and gate 20, it is possible, to erase, store (or program) and read two separate bits of information in each memory cell 10. FIGS. 2A-2C illustrate how memory cell 10 can be completely erased and how two separate bits can be separately programmed. To erase both bits (designated as right bit “bit-R”, and left bit “bit-L”), as shown in FIG. 2A, a negative voltage (e.g., −8V) is applied to gate 20 and positive voltages (e.g., 10 V) are applied to each of substrate 8, and source and drain regions 22, 24, such that electrons from the gate are injected substantially throughout nitride charge-trapping layer 16. As a result, charge-trapping layer 16 is effectively devoid of any holes.
To program bit-R of memory cell 10 (i.e., to trap holes toward the right hand side of charge-trapping layer 16), source region 22 is grounded, a positive voltage (e.g., 5 V) is applied to drain region 24 and a negative voltage (e.g., −5 V) is applied to gate 20. This biasing state causes hot hole injection to occur into nitride charge-trapping layer 16 in a region toward a drain-side of layer 16. Due to the nature of the nitride material, charge-trapping layer 16 is able to trap charges so that injected charges will not distribute evenly in the charge-trapping layer 16, but will instead be localized in a region of charge-trapping layer 16 near the charge injection side. Consequently, it is possible to program (i.e., positively charge) only one side of the charge-trapping layer at a time.
To program bit-L of memory cell 10, the voltages on source and drain regions 22, 24 are reversed (as compared to bit-R programming), as shown in FIG. 2C. Of course, although not shown, both bit-R and bit-L can be simultaneously programmed, or programmed successively such that both bit-R and bit-L are in a programmed state at the same time.
To read bit-L, for example, substrate 8 is either grounded or can be biased with a positive voltage, and a sensing voltage (e.g., 2-3 V) is applied to gate 20. A small positive voltage (e.g., 1.5-2 V) is then applied to drain 24, and source 22 is grounded. With the above voltages applied, the current in the source is sensed. (According to an alternative variation, the current in the drain is sensed.) Generally, the current in the drain is essentially zero if bit-L is not programmed. If bit-L is programmed, then a measurable current is observed in the drain. To be more precise, a “threshold” current is defined such that current is said to be present when the value of current exceeds the threshold value. When current does not exceed the threshold, then the current is declared to be zero. A typical value for threshold current is about 10 μA. The sensed value of current is compared with the threshold value. If the current does not exceed the threshold, a decision is made declaring that bit-L is not programmed. If the current exceeds the threshold, a decision is made declaring that bit-L is programmed.
To read bit-R, the small positive voltage (1.5-2 V) is applied to the source, while the drain is grounded and current is sensed.
FIGS. 3A and 3B show how a plurality of memory cells 10 can be arranged in a NAND string. Programming and reading are accomplished substantially the same way as described above, but instead of voltages being applied directly to the source and drain regions of a particular cell of interest, these voltages are instead applied to the ends of the given string (or bit-line) in which the cell of interest is located. The above-described appropriate gate voltage is applied to a wordline (WL) conductor, which is in electrical communication with the gate of the selected cell. Simultaneously, a Vpass voltage is applied to the wordlines (gates) of all other memory cells. The Vpass voltage effectively turns on the underlying transistor, allowing current to easily pass along the entire NAND string and for voltages applied at either end of the string effectively to be applied at the source and drain sides of the selected memory cell.
When operating a NAND string according to this manner, an undesirable phenomenon called “gate disturb” has been observed. Generally speaking, gate disturb is the undesirable injection of electrons into the nitride charge-trapping layer of a PHINES memory cell that corrupts the integrity of stored bits. As shown in FIG. 4, the higher the gate voltage (Vpass) and the longer the time such gate voltage (Vpass) is applied, a corresponding increase in Vt (the threshold voltage above which channel current is observed) is observed. This Vt “shift-up” is caused by the existence of a high vertical field that causes electrons to be injected into the nitride layer, resulting in decreased transport electrons in the channel. Also as shown by FIG. 4, more severe gate disturb is found as Vg (e.g., Vpass) increases (since the vertical field is larger) and the time over which Vg (or Vpass) is applied.
A similar gate disturb phenomenon has been observed when the NAND strings of FIGS. 3A and 3B are combined into a NAND array like that shown in FIG. 5. This figure shows that two different levels of gate disturb occur, one higher A and one lower B in the read operation, depending on the relative location of a cell with respect to the memory cell of interest.
Similarly, in the program operation of a NAND array as shown in FIG. 6, three different levels C, D, and E of gate disturb have been observed, with C representing higher gate disturb, and D and E representing lower levels of gate disturb. Note that one of the bit-lines in FIG. 6 shows two different biasing levels. When a biasing of 0 and 5 volts is applied to source and drain regions of a selected cell, one side of the selected cell is programmed (bit-R or bit-L), and when a biasing scheme of 0 and 3.5 volts is applied to source and drain regions of a selected cell, both bit-R and bit-L are not programmed.
In view of the above-described gate disturb problem, there is a need to improve the reliability of PHINES-type memory cells arranged in NAND strings and NAND arrays.